PERI

Owing to the failure of Dennard’s scaling, past decade has seen a steep growth prominent new paradigms leveraging opportunities in computer architecture. Two technologies interest are Posit and RISC-V. was introduced mid-2017 as viable alternative IEEE-754, RISC-V provides commercial-grade open source Instruction Set Architecture (ISA). In this article, we bring these two together propose Configurable Enabled Core called PERI. The article insights on how Single-Precision Floating Point (“F”) extension can be leveraged support posit arithmetic. We also present implementation details parameterized feature-complete Unit (FPU). configurability parameterization features unit generate optimal hardware, which caters accuracy energy/area tradeoffs imposed by applications, feature not possible with IEEE-754 implementation. FPU been integrated compliant SHAKTI C-class core an execution unit. To further leverage potential , enhance our different exponent sizes (with posit-size being 32-bits), thereby enabling multiple-precision at runtime. enable compilation C programs PERI, have made minimal modifications GNU Compiler (GCC), targeting “F” compare terms hardware area, application accuracy, alternate methodology integrating accelerator using custom opcode space